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MIPS Boosts MCU and Linux Cores

Tom Starnes, Analyst

November 2, 2009

MIPS Technology Inc. has been working on a more advanced version of the smallest instantiation of the MIPS core. The new MIPS M14K is the next step up from the prior M4K core destined for microcontrollers and area-constrained chips. This alone is perhaps the most significant part of the recent announcement – the M4K wasn't a single point in the architecture, but the beginning of a branch of the tree. That's always the implication, but even biological trees have branches that wither away when they are disused or ineffective.

MIPS 32-bit Processor Core FamiliesFigure 1. MIPS 32-bit Processor Core Families   
(all illustrations from MIPS Technology)(click to enlarge)  

In many ways the related press release announces the development of the architecture and then parades a variety of chip, OS, and development tool vendors through the document saying what a great idea it is and that they'll probably support it. We'll have more on this topic in a moment.

MIPS Saves 35% on a Thumb Job

What exactly is more advanced about the M14K? Details are still sketchy, but the big item is a new microMIPS instruction set architecture (ISA). It looks like MIPS read ARM's Thumb2 handbook and similarly performed a sort on the use of the MIPS instruction set, really prioritizing instructions and squeezing the most-used ones into less program memory. The problem with this can be delays in decoding and executing, but it is not too hard to come out ahead when you're fetching two 16-bit instructions with the same 32-bit memory fetch as before, as long as programs progress as expected. It's a little trickier for pipelined RISC processors than the old hardy CISCs, but the overall advantages are still very good.

The numbers for microMIPS are reported as 35% smaller code space while requiring maybe 2% more time to execute, which should be a no-brainer tradeoff for the most part. This is roughly on par with comparisons of Thumb2 to full 32-bit ARM - five years ago. This also makes a person think any 32-bit architecture could squeeze 35% out of its code space with compression. Maybe this figure describes the best-case code expansion one would typically find when moving from a 16-bit MCU to a 32-bit MCU.

Compatibility Plus

To take advantage of the compressed microMIPS instructions, programs will need to be recompiled. Is that old, familiar compatibility dance music playing now? Well, no. Original MIPS32 code will run through the new M14K cores as well as the new 16-bit encodings. Even a few new 32-bit instructions are included to add new capabilities.

This brings up the one significant difference between the microMIPS engine and ARM's Thumb2. The microMIPS processor will execute both traditional MIPS32 instructions and the new compressed 16-bit instructions (no mode switch, either). The ARM cores that run the Thumb2 instructions will only run Thumb2 and cannot handle ARM7 instructions. This means when moving to a Thumb2 core, all existing ARM code must be recompiled and verified. However, moving from another MIPS32 core to a microMIPS core allows the original binaries to execute, or desired sections of code can be recompiled into microMIPS instructions to gain the memory space advantage. This sounds like compatibility at its best.

Memory Advantages for a Little Linux

MIPS has also announced a second core - adding a "c" to the designation. Like the earlier MIPS 4KEc core, the new M14Kc adds an enhanced memory system to the core with memory management and cache control easing access to large memory systems for the new microMIPS execution unit. If Linux or a more sophisticated system is your game, then the M14Kc should get your mouth watering. Block diagrams of the M14K and the M14Kc are presented in Figure 2.

Memory Interfaces  Figure 2. Block Diagrams showing the memory interface
  differences between MIPS M14K and M14Kc

MIPS Runs With the Small Dogs

A few years ago MIPS revealed the very small MIPS M4K core, designed for integration in microcontrollers and similar products where only low performance is needed and die size is truly at a premium. The M4K is ideal in such applications that might otherwise make use of proprietary processor cores, "configurable cores" like ARC or Tensilica, purpose-built "just put something in there as long as it's free" processors like the FPGA vendors offer, or – most feared – an ARM7, ARM Cortex-M3 or -M0 core might be used.

MIPS needed to be sure its instruction set architecture (ISA) is considered for such core opportunities and the M4K opened that door. But no processor architecture can stand still when greater performance, lower power, different configurations, newer process nodes, and extended –and sometimes constrained – operations are evolving in the marketplace. Plus, an IP (intellectual property) company needs extensions to their product line for reasons somewhat different than the reasons chip manufacturers need product extensions.

MIPS Technology is clearly targeting ARM alternatives for the new M14K and M14Kc, making direct comparisons to the ARM Cortex-M3 and ARM 926 in its literature. Target markets for the new MIPS cores also overlay ARM success areas. There are possibilities for MIPS. The company claims nearly double the performance, half the core size, or three-quarters the power of designated ARM cores, depending on which process corner the processor is pushed into and for what node. Advantages for the M14Kc are more in the range of 15%-25%. Comparisons provided by MIPS can be found in Figure 3.M14 Comparison to ARM

Figure 3. Comparisons by MIPS Technology of
MIPS M14K, M14Kc, ARM Cortex-M3, and ARM926

The real question of MIPS vs. ARM comes down to just familiarity. Are you an experienced MIPS developer or a designer familiar with ARM? Is the ecosystem for ARM more favorable than that for MIPS in your application area? For so many applications these days, ARM is the good choice, and increasingly so. There are easily five major MCU vendors which are earnestly backing the ARM Cortex-M3. So far there is only one traditional MCU vendor backing the new MIPS architecture: Microchip. Those numbers are pretty easy to compare, and that is a very reasonable comparison.

The Place to Buy M14K

Microchip Technology (MCHP) was the first MCU supplier to endorse the MIPS M4K architecture with a spread of 32-bit microcontrollers. This was a curious choice at the time in light of the ARM CortexM3 architecture which had already found a number of corporate followers. However, Microchip proclaimed significant performance advantages over the Cambridge-based company's cores, and this is backed by the CoreMark/MHz ratings ( Microchip also proclaimed size and power benefits, and marched on. The company seems to be alone in that level of commitment to a MIPS MCU. The MIPS M14K announcement includes words from Microchip, but a close read reveals that they're not firm commitments.

While this analyst fully expects MCHP to roll out M14K MCUs in the future, Microchip is not ready to say "I do," or even "I would like to," but is saying more "she sure is pretty."

However, the M14K core is not fully formed, and Microchip likes to have the breach locked and loaded before making chip introductions, so this may not be untoward. Surely Microchip will offer its customers the advantages offered by the upgraded MCU core. Whether any other microcontroller vendor will offer off-the-shelf MCUs based on the M4K or M14K seems to still be an open question.

MIPS Strategy

It is curious, probably planned, that the announcement of the new MIPS cores comes barely a week after ARM's annual developer conference, now called ARMtechcon3. There was no indication at the ARM conference that anyone was concerned about the MIPS architecture overall, and there has been little ARM-waving about the new microMIPS extension since.

The way the M14K's fit in MIPS's architecture map can be seen in Figure 1. It's particularly nice that saying "M14K" rolls off the tongue as easily as M4K and one almost thinks they might be related. The next hitch in the name game is already essentially occupied (24K) but we'll let MIPS be creative there later. "MicroMIPS" is a cute name with various connotations, but the architecture name, MIPS, from day one was an incarnation of a common industry acronym, so lawyers and engineers will continue to dance around what is and is not misuse. Is a microMIPS one one-millionth(micro) (10-6) of a million instructions per second(MIPS), er, is that one IPS? Is a microMIPS as powerful as a MIPS(architecture) MIPS(instr/sec)? And don't get me going on the value of Dhrystone MIPS(DMIPS) in measuring performance. That's why we have EEMBC.

While MIPS has been a bit distracted the last few years rounding up analog IP and watching their mainstay markets be encroached upon, it has been a while since we've seen processor announcements or new uses of the MIPS architecture. It's good to see them back in the game.

Compression Gives a Prime 32-bits the Figure of a 16-bitter

There are many tradeoffs of 8-bit, 16-bit, and 32-bit processors in microcontrollers. Code compression is an attempt to make 32-bit processors look as skinny as 16-bit MCUs in the memory it requires. The original 16-bit Thumb instructions are one of the features that let the ARM7 become such a smash hit in cost-sensitive mobile phones and other embedded applications. Most architectures came out with similar compression techniques shortly after seeing the draw of Thumb in shrinking code.

Methods varied, with two techniques offered by the major purveyors of PowerPC, an earlier approach by MIPS in MIPS16, and whole architectures designed to be ARM-killers, with limited real success. Ultimately, if there are only 8 operations from which all functions can be built, a 3-bit encoding is all that is necessary. One of the original tenets of RISC was to use the simplest operations. But it then takes long strings of these operations to do something, which can mean a lot of code space.

Meantime, where 32-bits allows a huge variety of operations, adding register 1 to register 2 could take just 3 bits to specify as easily as it takes 32. And even with today's very dense process technology, 10x the memory can be costly. Balancing the variety with the memory requirements is the name of the game in compression. Recouping a big chunk of that memory can be very advantageous.

MIPS Marches Forward in Micro Chips

The MIPS M14K and M14Kc are attractive cores and should keep the low end of the architecture alive and well. The extent to which this extends MIPS's reach in embedded applications seems to rest on the shoulders of Microchip Technology. From the other side, Microchip will get an upgrade to its chosen 32-bit MCU core without having to shell out the heavy investment that companies using more-proprietary MCU processors must. But the legion of ARM core users will continue to provide a strong head-wind in this broad market.

-Tom Starnes